- The intention of the project was to be able to load-balance the various flows in a pseudo wire emulation across various equal cost multi paths. This will enable the customers to be able to serve high bandwidth customers.
- Implementation of the feature is based on the IETF rfc6391.txt
Flow-Aware Transport of Pseudo wires over an MPLS Packet Switched Network
- Flow aware tansportpeudo wire emulation defines using a flow label to achieve load balancing.
- Pseudo wires based on label distribution protocol (LDP) and LDP over RSVP need to be supported.
- The traffic coming on a pseudo wire needs to be load-balanced across the various ECMP paths such that the packets of the same flow always follow the same path with packet order intact.
- Ingress nodes should add flow label, transit nodes send flow label as if and egress nodes strip.
- The feature should support regular features such as high availability, hitless image upgrade, etc.
- Support for VCCV LSP ping.
- ECMP paths can go over LAG.
- VPLS circuit support.
- The challenge was to understand the control and data plane code and add support for the above featurefor VPLs, ECMP circuits, image upgrades, high availability, circuit bundles, LSP over LAG, vccv ping, etc.
- Technology was new to Benison as the team was working on this for the first time.
- Benison exposure to control and data plane software was quite limited.
- Benison studied the control and data plane code, provided detailed design to add support for FAT featurefor VPLS, ECMP circuits, image upgrades, high availability, circuit bundles, LSP over LAG, vccv ping, etc.
- In the process it also had to maintain the legacy support for these features.
- The feature is being implemented within estimated time frame.