- Network Processors (NPU’s) provides the wire speed packet processing. A combination of internal and external TCAM’s and RAM’s provide the NPU’s with an unprecedented amount of lookups per packet and at the same time large tables, and support millions of counters and meters.
- One of RAM interface with NPU is brought up to read/write data at packet processing speed.
- This helps to achive the overall system packet processing rate.
- Design and develop the interface between NPU and FPGA.
- FPGA device should be able to control through NPU using microcode.
- Develop microcode functions to generate commands necessary to perform look aside bus training.
- Should be able to initiate and complete BIST test of RAMs.
- It should be ability to execute the various write/read commands to/from the FPGA via a PC or by other means is required.
- The interface with SRAM should be first initialized and calibrated between NPU and MUX FPGA which is used to do read/write multiple RAMS over single interface.
- The interface should be able to read write at all corresponding RAMS and provide the data with in prescribed time limits.
- All internal control and status register read write should work to calibrate the FPGA.
- Initialization sequence of the interface and MUX FPGA is done and confirmed using status registers.
- Calibrated the interface by generating the patterns over data bus between NPU and FPGA.
- Maintained the data rate.(Number of clocks per read write within prescribed limit)
- Algorithm is developed to adjust the DLL values.